The 3nm competition is heating up

Advanced manufacturing process is very popular, and it is the focus of the industry almost every year. Although there are very few chip products that really need advanced manufacturing process, this does not prevent advanced manufacturing process from becoming the target of TSMC, Samsung, Intel and other chip giants. After all, for the entire semiconductor industry, advanced technology is the most critical technical reserve.

In 2022, the advanced process will officially move to 3nm. In the first half of the year, Samsung announced mass production of 3nm, becoming the first manufacturer in the world to start mass production of 3nm chips. Now 2022 has ushered in the last quarter, and the 3nm competition seems to have entered a white-hot stage.

Mass production delay? N3E chip tape out? How is TSMC progressing?

TSMC, as the world’s leading wafer foundry company, is expected to replace Samsung and Intel and become the real global semiconductor leader with sales of NT$613.1 billion in the third quarter not long ago, but its 3nm chips have not yet been officially mass-produced. There are even Korean media reports that TSMC’s 3nm mass production schedule has been delayed by three months. The reason is that in a recent conference call, TSMC said that 3nm chips will start mass production in the fourth quarter of this year. Mass production started around the end of September, 3 months later. In this regard, Taiwanese media Economic Daily stated in the article “Rebutting Korean Media… 3nm Q4 Mass Production” that industry insiders pointed out that the reason why Korean media used the word “re-delay” should be the same as TSMC’s original statement of “3nm Q4”. It is related to the statement that mass production is expected in the second half of 2022. Korean media may think that “the second half of 2022” refers to “July”, but the fourth quarter also falls in the second half of the year, so TSMC’s 3nm does not matter about the delay. production problem.

Although there was an oolong “mass production delay”, it did not affect TSMC’s 3nm entering the sprint stage. TSMC has made it clear that its 3nm has high yields and that customer N3 demand has exceeded TSMC’s supply capacity, partly from machine delivery issues.

Source: Business Times

In addition, TSMC also expects that N3 will reach full utilization in 2023. Compared with N5’s first year of mass production in 2020, it is expected that N3 will contribute more revenue in 2023, while TSMC’s overall revenue base will be higher than in 2020. Huge, the N3 process is expected to account for 4% to 6% of wafer revenue next year.

N3 is TSMC’s first-generation 3nm technology. Previously, because TSMC rarely disclosed N3-related news at the 2022 technical seminar, and some bloggers said that due to the high cost, both TSMC and Apple decided to give up the N3 process, which made people feel uncomfortable. It was once thought that the N3 node would become an “abandoned child”. However, from the current point of view, N3 is still the process node that TSMC focuses on.

And the N3E node, which is considered to be the mainstream of TSMC’s 3nm process, has good news of tape-out recently. On October 24, Alphawave IP announced the successful tapeout of its first test chip using TSMC’s most advanced N3E process. As an extension of TSMC’s 3nm family, N3E has better performance, power consumption and yield. Based on N3E, TSMC has also derived four variants of N3P, N3X, N3S and N3RF. TSMC revealed that the development progress of N3E technology is ahead of schedule, and mass production is expected in the second half of 2023.

Source: TSMC

In addition, TSMC also reflects the emphasis on 3nm in terms of capital expenditure and personnel layout. For example, in the face of an uncertain future, although TSMC has chosen to reduce capital expenditures from US$44 billion at the beginning of the year to US$36 billion, the main reason is to delay the expansion of 7nm production, and the construction of new 3nm production capacity and the timetable for mass production still remain. Maintain the original plan. Including the internal letter from Wei Zhejia of TSMC, although employees are encouraged to take more rest, it also clearly points out that 3nm, which is about to be mass-produced, and personnel related to the R&D process below 3nm are not included. It can be seen that for 3nm, TSMC has entered the sprint stage.

On the whole, TSMC is very optimistic about the future of 3nm, and pointed out that although the inventory adjustment continues, both N3 and N3E have many customers participating, and the number of product design decisions in the first and second years of mass production will be more than twice that of N5. . As 3nm production capacity will be launched quarter by quarter next year, major customers including Apple, Intel, and Qualcomm will also introduce mass production, which will become the main driving force for TSMC’s revenue growth in 2023 compared with this year. According to “Bloomberg” technology reports, Apple’s new M2 chip processor is more likely to monopolize the large order of TSMC’s 3nm foundry.

Expanding outsourcing and increasing production capacity, Samsung is stepping up

Samsung and TSMC have been chasing me for more than ten years in the field of advanced manufacturing. As the founder of foundry, TSMC has been occupying half of the country since its establishment. There is indeed a significant performance gap, and it is not easy for Samsung to catch up or even surpass. In 2015, Samsung won a part of Apple’s orders with 14nm, but that time, the corner overtaking did not make Samsung’s foundry to a higher level, but fell into a performance storm, and thus completely lost Apple’s generation work order.

The first mass production of 3nm this year is another overtake by Samsung. The news shows that Samsung’s 3nm GAA chip was put into production on June 30 and officially shipped on July 25. Compared with the 5nm chip, the power consumption of Samsung’s 3nm chip is reduced by 45%, the performance is improved by 23%, and the area is reduced by 16%. Samsung promises to greatly improve chip energy efficiency with the help of GAA technology. If Samsung’s 3nm performance and yield can achieve satisfactory results, then Samsung can make a beautiful turnaround. Orders will naturally increase accordingly, which is of great help in increasing market share.

However, Taiwanese media have always been skeptical of Samsung’s 3nm, thinking that even if Samsung takes the lead in mass production, it will not benefit from it. TrendForce data shows that Samsung’s 3nm process adopts GAA architecture technology, and most of its customers are Chinese enterprises. Due to the existence of the US ban, Chinese manufacturers are restricted from using EDA to design GAA architecture technology chips. When Chinese customers cannot design 3nm GAA architecture chips, they are handed over to Samsung. Foundry, on behalf of the limited contribution of Samsung’s 3nm process. However, in the face of these doubts, Samsung does not seem to care. The article “Samsung Semiconductors, Full of Vitality” can be seen that Samsung has made full efforts from equipment materials, IC substrates, advanced packaging, and wafer fab expansion. Recently, Samsung Another series of radical layouts.

The first is that Samsung plans to increase the outsourcing of non-memory chip production. Some chips that can be produced by traditional processes below 14nm, such as image sensors, are entrusted to foundries such as TSMC, Power Electromechanical, and World Advanced. Samsung’s idea is to enhance the stability of chip procurement through diversification of supply sources.

Second, Samsung Electronics is also exploring options for developing and operating new foundry production lines in Europe and other places. Analysts believe that Samsung Electronics’ move is a mid-to-long-term layout to explore “third factories” outside of scheduled production lines such as Pyeongtaek in South Korea and Taylor in the United States. Samsung Securities stated in its July report that it is necessary to consider setting up a semiconductor foundry in Europe. In addition, Samsung also plans to actively strive for the foundry market in the United States. In addition to the factory in Austin, Texas, it is also planning to build a new factory in nearby Tyler City. It is expected to start operation in 2024 and provide foundry mass production with the latest 3nm process technology. resource.

Samsung has spared no effort to expand its foundry capacity because Choi Si-young, president of Samsung’s foundry business unit, made it clear at a recent event that Samsung’s goal in 2027 is to more than triple its production capacity. To this end, Samsung has implemented a “Shell First” strategy, which is to build clean rooms first, and then operate flexibly when market demands arise. It is understood that Samsung has operated five factories in South Korea and the United States, and has acquired sites to build more than 10 fabs.

Source: Samsung

Like TSMC, Samsung also revealed the second and even third-generation 3nm technology progress, not only will GAA transistors be smaller in size, but also more efficient. Among them, the transistors of the second-generation 3nm chip (SF3) will be 20% smaller than the first-generation 3nm. It is expected to be launched in 2024. Samsung plans to further improve the 3nm transistor manufacturing technology through the SF3P+ process, and start mass production of 2nm chips in 2025. .

Intel sticks to Moore’s Law

Since Intel was taken over by Pat Gelsinger last year, foundry seems to have become the focus of its efforts. In order to restore the lost advanced process leadership, Intel announced a series of large-scale investments to build new advanced process wafers in the United States, Germany and other places. Round factory, and acquired Tower Semiconductor, a large Israeli foundry.

Intel has always adhered to Moore’s Law. At the second Intel On Technology Innovation Summit, Pat Gelsinger said that Moore’s Law “is alive and well.” Starting today, we aspire to contain about 100 billion transistors in one package, By the end of the century, the number of transistors in a single package will reach a trillion, and Intel is on schedule.

According to Intel’s process roadmap, Intel 7 is being produced and shipped in batches, and Intel 4 will use EUV technology. It is expected to be put into production in the second half of 2022, and its transistor performance per watt will increase by about 20%; while Intel 3 is an Intel foundry. The focus of the service will be to provide I/O Fin and high-density cells, as well as more EUV use and better transistors and interconnects, with about 18% improvement in performance per watt, with production expected in the second half of 2023.

Source: Intel

In order to better realize IDM 2.0, Intel also announced a new chip foundry model consisting of four main parts: wafer manufacturing, packaging, software and chiplet ecosystem, and strives to “system-level foundry”. Intel even launched the $1 billion IFS Innovation Fund to support early-stage startups and established companies building disruptive technologies for the foundry ecosystem.

Just recently, Intel also established a new foundry alliance, the USMAG (United States Military, Aerospace and Government) Alliance, as a strategic addition to its design ecosystem accelerator program, with initial members including Cadence, Synopsys, Siemens Digital Chip giants such as Industries Software, Intrinsix and Trusted Semiconductor Solutions. Just this February, Intel Foundry Services (IFS) launched its Accelerator Design Ecosystem program to help foundry customers take silicon products from idea to implementation.

Regarding the new progress of advanced process development, Intel clearly stated that the Intel 18A test chip is under design and will be trial-produced by the end of this year, and emphasized that the advanced process is progressing smoothly, even exceeding expectations, and will launch 5 advanced process generations within 4 years.

Where to go in the future

3nm is of course the focus of today, but the semiconductor industry has developed so far, as people have higher and higher requirements for chip performance and more and more transistors, how will Moore’s Law continue? What kind of efforts have chip giants such as TSMC, Samsung, and Intel made in order to promote the process to a more advanced aspect?

Backside power supply is one of the new technologies that must be mentioned. At present, TSMC, Samsung, and Intel have all determined to use this technology in future advanced manufacturing processes. Backside powering involves moving power lines on a chip to the vacant backside of the wafer, freeing up more space for signal paths above the transistor layers, allowing more transistors to squeeze into the same area of ​​the silicon. The “backside power network” will bypass 12 or more wiring layers of the chip to reduce the voltage by a factor of up to seven, Applied material said.

At present, Intel has listed its backside power supply technology called “PowerVia” as one of the three major process innovations. As the industry’s first new backside power transmission network, PowerVia can use metal more efficiently by separating power supply and signal. layer to improve performance; TSMC will use backside power supply technology in later versions of the N2 node; and according to TheLec report, Samsung also plans to use the backside power supply network for the 2nm process technology.

Source: TheLec

The second is the new transistor structure. Currently, in terms of the 2nm process, TSMC, Samsung and Intel have clearly adopted the GAA structure. Among them, TSMC expects that 2nm will enter risky trial production in the second half of 2024 and enter mass production in 2025. The factory area is bamboo The Fab 20 ultra-large fab in the second phase of Kebaoshan is planned to build four 12-inch fabs; Samsung is expected to start producing 2nm chips in 2025 and mass production of 1.4nm chips in 2027; Intel’s Intel 20A is expected to It will be put into production in the first half of 2024, and will achieve about 15% improvement in performance per watt through RibbonFET (GAA) and PowerVia technologies, and open the era of Ami.

In addition, Samsung and IBM announced breakthroughs in new vertical transfer field effect transistors (VTFETs) late last year. This new type of transistor allows vertical current flow and the ability to place more transistors on a given surface, creating more contact points for transistors for greater energy flow and less waste. Compared to existing FinFET transistors, VTFETs can reduce chip energy by 85 percent and double FinFET chip performance.

Another is advanced packaging technology. At present, 3DFabric advanced packaging has become a new field targeted by TSMC. In order to accelerate the 3D Fabric ecosystem, TSMC established the 3DFabric Alliance, including Micron, Samsung, and SK Hynix, 19 partners have agreed to join the alliance. According to TSMC’s plan, its advanced packaging production capacity in 2026 is expected to expand 20 times compared to 2018.

Intel demonstrated its breakthrough in pluggable optoelectronic co-package solutions at the 2022 Intel Innovation Conference recently. It is reported that Intel researchers have designed a robust, high-yield, glass-based solution that simplifies the manufacturing process and reduces costs through a pluggable connector, opening the door to new system and chip packaging architectures in the future. New possibilities.

Samsung Si-young Choi said at the Samsung Foundry Forum also held recently that Samsung will accelerate 2.5D/3D heterogeneous integrated packaging technology to provide systematic foundry service solutions. According to its introduction, Samsung’s X-Cube 3D packaging technology using micro-bump connection will be ready for mass production in 2024, and the bumpless X-Cube packaging technology will come out in 2026.

The other is two-dimensional materials. TSMC engineers, in collaboration with two universities in Taiwan, will report the world’s first nanosheet gate-ring transistor made of a two-dimensional semiconductor material at this year’s International Conference on Electronic Devices (IEDM). According to the highlights of an upcoming IEDM program, TSMC has demonstrated the possibility of using transition metal dichalcogenide monolayers as semiconductor channels in nanosheet transistors.

In addition, TSMC has also cooperated with National Taiwan University and the Massachusetts Institute of Technology to find that two-dimensional materials combined with “semi-metal bismuth (Bi)” can achieve extremely low resistance, close to the quantum limit, and help achieve semiconductor process challenges below 1nm. According to the news, the technical research department of TSMC optimized the bismuth (Bi) deposition process, and the NTU team used a helium ion beam lithography system to successfully reduce the component channel to nanometer size, and finally achieved a breakthrough research result.

It can be seen that although 2nm, 1nm and other advanced processes have been 3 years or even 5 years later, chip giants have already begun to develop new technologies in advance, although who will gain the leading position in the future is not easy for us now It is predicted, but it can be confirmed that Moore’s Law will not die easily. Even if future technology research and development will become more and more difficult, there will always be people who will use new technologies to “extend their lives”.