Abstract: On October 27, Alphawave, a network chip design company, announced that its ZeusCORE100 1-112Gbps NRZ / PAM4 has been successfully taped out. The chip will support many standards including 800G Ethernet, OIF 112G-CEI, PCIe 6.0 and CXL3.0, and it is also the first test chip for TSMC’s 3nm family N3E process.
On October 27, Alphawave, a network chip design company, announced that its ZeusCORE100 1-112Gbps NRZ / PAM4 has been successfully taped out. The chip will support many standards including 800G Ethernet, OIF 112G-CEI, PCIe 6.0 and CXL3.0, and it is also the first test chip for TSMC’s 3nm family N3E process.
Alphawave is also expected to be the first customer for TSMC’s N3E process. The chip has now passed all necessary tests and is expected to be showcased at TSMC’s OIP Forum.
Alphawave CEO Tony Pialis said he is proud to be one of the first companies to use TSMC’s most advanced N3E process technology, and the partnership will continue to bring innovative high-speed connectivity technologies to power the most advanced data centers.
According to TSMC’s previous official statement, comparing N3 and N5 process technologies, N3 is expected to bring a 10% to 15% performance improvement under the same power number and complexity, or a reduction in the same frequency and number of transistors 25%-30% power consumption while increasing logic density by about 1.6 times.
As for the updated N3E, TSMC’s second-generation 3nm node process technology, compared with the N5 node process, the performance improvement is about 18%, or the power consumption is reduced by 34%, and the logic density is increased by about 1.7 times. Compared with the first-generation N3 process technology, TSMC expects that N3E will be more widely adopted, and the mass production time is mid-2023 or the third quarter.
In fact, from 2022 to 2025, TSMC will successively launch 3nm node processes such as N3, N3E, N3P, N3X, etc. It is also expected to have an optimized N3S process in the future, which can cover smartphones, Internet of Things, automotive chips, high-tech The usage requirements of different platforms such as performance computing.
TSMC still uses FinFET finFET architecture technology on the N3 node process, but can use FINFLEX technology to expand the performance, power and density range of the process technology, allowing chip designers to use the same design tools. Choose the best option for each key function block to further improve the PPA (power, performance, area).
Editor: Xinzhixun-Linzi Source: technews